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168 lines
6.2 KiB
C
168 lines
6.2 KiB
C
/* $Id: z8530reg.h,v 1.3 2003/10/25 17:07:58 fredette Exp $ */
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/* ic/z8530reg.h - register definitions for Zilog 8530 emulation: */
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/*
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* Copyright (c) 2003 Matt Fredette
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Matt Fredette.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _TME_Z8530REG_H
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#define _TME_Z8530REG_H
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#include <tme/common.h>
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_TME_RCSID("$Id: z8530reg.h,v 1.3 2003/10/25 17:07:58 fredette Exp $");
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/* macros: */
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/* WR0: */
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#define TME_Z8530_WR0_CRC_RESET_MASK (0xc0)
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#define TME_Z8530_WR0_CRC_RESET_NULL (0x00)
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#define TME_Z8530_WR0_CRC_RESET_RX (0x40)
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#define TME_Z8530_WR0_CRC_RESET_TX (0x80)
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#define TME_Z8530_WR0_CRC_RESET_TX_EOM (0xc0)
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#define TME_Z8530_WR0_CMD_MASK (0x38)
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#define TME_Z8530_WR0_CMD_NULL (0x00)
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#define TME_Z8530_WR0_CMD_POINT_HI (0x08)
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#define TME_Z8530_WR0_CMD_RESET_STATUS (0x10)
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#define TME_Z8530_WR0_CMD_SEND_ABORT (0x18)
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#define TME_Z8530_WR0_CMD_INT_NEXT_RX (0x20)
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#define TME_Z8530_WR0_CMD_RESET_TX (0x28)
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#define TME_Z8530_WR0_CMD_RESET_ERROR (0x30)
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#define TME_Z8530_WR0_CMD_RESET_IUS (0x38)
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#define TME_Z8530_WR0_REGISTER_POINTER (0x07)
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/* WR1: */
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/* for now we ignore the DMA-related bits: */
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#define TME_Z8530_WR1_RX_INT_MASK (0x18)
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#define TME_Z8530_WR1_RX_INT_DISABLE (0x00)
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#define TME_Z8530_WR1_RX_INT_1ST_SPCL (0x08)
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#define TME_Z8530_WR1_RX_INT_ALL_SPCL (0x10)
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#define TME_Z8530_WR1_RX_INT_SPCL (0x18)
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#define TME_Z8530_WR1_PARITY_SPCL (0x04)
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#define TME_Z8530_WR1_TX_INT_ENABLE (0x02)
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#define TME_Z8530_WR1_STATUS_INT_ENABLE (0x01)
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/* WR3: */
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#define TME_Z8530_WR3_RX_CSIZE_MASK (0xc0)
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#define TME_Z8530_WR3_RX_CSIZE_5 (0x00)
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#define TME_Z8530_WR3_RX_CSIZE_7 (0x40)
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#define TME_Z8530_WR3_RX_CSIZE_6 (0x80)
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#define TME_Z8530_WR3_RX_CSIZE_8 (0xc0)
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#define TME_Z8530_WR3_AUTO_ENABLES (0x20)
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#define TME_Z8530_WR3_HUNT (0x10)
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#define TME_Z8530_WR3_RX_CRC_ENABLE (0x08)
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#define TME_Z8530_WR3_ADDRESS_SEARCH (0x04)
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#define TME_Z8530_WR3_SYNC_LOAD_INHIB (0x02)
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#define TME_Z8530_WR3_RX_ENABLE (0x01)
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/* WR4: */
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#define TME_Z8530_WR4_CLOCK_X_MASK (0xc0)
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#define TME_Z8530_WR4_CLOCK_X1 (0x00)
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#define TME_Z8530_WR4_CLOCK_X16 (0x40)
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#define TME_Z8530_WR4_CLOCK_X32 (0x80)
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#define TME_Z8530_WR4_CLOCK_X64 (0xc0)
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#define TME_Z8530_WR4_SYNC_MASK (0x30)
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#define TME_Z8530_WR4_SYNC_8BIT (0x00)
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#define TME_Z8530_WR4_SYNC_16BIT (0x10)
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#define TME_Z8530_WR4_SYNC_SDLC (0x20)
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#define TME_Z8530_WR4_SYNC_EXTERNAL (0x30)
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#define TME_Z8530_WR4_STOP_MASK (0x0c)
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#define TME_Z8530_WR4_STOP_SYNC (0x00)
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#define TME_Z8530_WR4_STOP_1BIT (0x04)
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#define TME_Z8530_WR4_STOP_1_5BITS (0x08)
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#define TME_Z8530_WR4_STOP_2BITS (0x0c)
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#define TME_Z8530_WR4_PARITY_EVEN (0x02)
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#define TME_Z8530_WR4_PARITY_ENABLE (0x01)
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/* WR5: */
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#define TME_Z8530_WR5_DTR (0x80)
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#define TME_Z8530_WR5_TX_CSIZE_MASK (0x60)
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#define TME_Z8530_WR5_TX_CSIZE_5 (0x00)
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#define TME_Z8530_WR5_TX_CSIZE_7 (0x20)
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#define TME_Z8530_WR5_TX_CSIZE_6 (0x40)
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#define TME_Z8530_WR5_TX_CSIZE_8 (0x60)
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#define TME_Z8530_WR5_BREAK (0x10)
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#define TME_Z8530_WR5_TX_ENABLE (0x08)
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#define TME_Z8530_WR5_SDLC_CRC16 (0x04)
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#define TME_Z8530_WR5_RTS (0x02)
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#define TME_Z8530_WR5_TX_CRC_ENABLE (0x01)
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/* WR9: */
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#define TME_Z8530_WR9_RESET_MASK (0xc0)
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#define TME_Z8530_WR9_RESET_NULL (0x00)
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#define TME_Z8530_WR9_RESET_CHAN_B (0x40)
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#define TME_Z8530_WR9_RESET_CHAN_A (0x80)
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#define TME_Z8530_WR9_RESET_CHIP (0xc0)
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#define TME_Z8530_WR9_SOFT_INTACK (0x20)
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#define TME_Z8530_WR9_INTVEC_STATUS (0x10)
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#define TME_Z8530_WR9_MIE (0x08)
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#define TME_Z8530_WR9_DLC (0x04)
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#define TME_Z8530_WR9_NV (0x02)
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#define TME_Z8530_WR9_VIS (0x01)
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/* WR15: */
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#define TME_Z8530_WR15_BREAK_IE (0x80)
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#define TME_Z8530_WR15_TX_EOM (0x40)
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#define TME_Z8530_WR15_CTS_IE (0x20)
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#define TME_Z8530_WR15_SYNC_HUNT_IE (0x10)
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#define TME_Z8530_WR15_DCD_IE (0x08)
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#define TME_Z8530_WR15_SDLC_FIFO_ENABLE (0x04)
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#define TME_Z8530_WR15_ZERO_COUNT_IE (0x02)
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/* RR0: */
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#define TME_Z8530_RR0_BREAK (0x80)
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#define TME_Z8530_RR0_TX_UNDER_EOM (0x40)
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#define TME_Z8530_RR0_CTS (0x20)
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#define TME_Z8530_RR0_SYNC_HUNT (0x10)
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#define TME_Z8530_RR0_DCD (0x08)
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#define TME_Z8530_RR0_TX_EMPTY (0x04)
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#define TME_Z8530_RR0_ZERO_COUNT (0x02)
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#define TME_Z8530_RR0_RX_AVAIL (0x01)
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/* RR1: */
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#define TME_Z8530_RR1_END_OF_FRAME (0x80)
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#define TME_Z8530_RR1_ERROR_FRAME (0x40)
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#define TME_Z8530_RR1_ERROR_RX_OVERRUN (0x20)
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#define TME_Z8530_RR1_ERROR_PARITY (0x10)
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#define TME_Z8530_RR1_RESID_0 (0x08)
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#define TME_Z8530_RR1_RESID_1 (0x04)
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#define TME_Z8530_RR1_RESID_2 (0x02)
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#define TME_Z8530_RR1_ALL_SENT (0x01)
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/* RR3: */
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#define TME_Z8530_RR3_CHAN_A_IP_RX (0x20)
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#define TME_Z8530_RR3_CHAN_A_IP_TX (0x10)
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#define TME_Z8530_RR3_CHAN_A_IP_STATUS (0x08)
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#define TME_Z8530_RR3_CHAN_B_IP_RX (0x04)
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#define TME_Z8530_RR3_CHAN_B_IP_TX (0x02)
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#define TME_Z8530_RR3_CHAN_B_IP_STATUS (0x01)
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#endif /* !_TME_Z8530REG_H */
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