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244 lines
9.6 KiB
C
244 lines
9.6 KiB
C
/* $Id: sun3-impl.h,v 1.4 2009/08/30 14:19:55 fredette Exp $ */
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/* machine/sun3/sun3-impl.h - implementation header file for Sun 3 emulation: */
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/*
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* Copyright (c) 2003, 2004 Matt Fredette
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Matt Fredette.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MACHINE_SUN3_IMPL_H
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#define _MACHINE_SUN3_IMPL_H
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#include <tme/common.h>
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_TME_RCSID("$Id: sun3-impl.h,v 1.4 2009/08/30 14:19:55 fredette Exp $");
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/* includes: */
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#include <tme/generic/bus.h>
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#include <tme/machine/sun.h>
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#include <tme/ic/m68k.h>
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#include <tme/element.h>
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/* macros: */
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/* real sun3 control space addresses: */
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#define TME_SUN3_CONTROL_IDPROM (0x00000000) /* the IDPROM */
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#define TME_SUN3_CONTROL_PGMAP (0x10000000) /* the page map */
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#define TME_SUN3_CONTROL_SEGMAP (0x20000000) /* the segment map */
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#define TME_SUN3_CONTROL_CONTEXT (0x30000000) /* the context register */
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#define TME_SUN3_CONTROL_ENABLE (0x40000000) /* the enable register */
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#define TME_SUN3_CONTROL_UDVMA (0x50000000) /* the user DVMA enable register */
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#define TME_SUN3_CONTROL_BUSERR (0x60000000) /* the bus error register */
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#define TME_SUN3_CONTROL_DIAG (0x70000000) /* the diagnostic register */
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#define TME_SUN3_CONTROL_VAC_TAGS (0x80000000) /* the VAC tags */
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#define TME_SUN3_CONTROL_VAC_DATA (0x90000000) /* the VAC data */
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#define TME_SUN3_CONTROL_VAC_FLUSH (0xa0000000) /* the VAC flush address */
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#define TME_SUN3_CONTROL_COPY (0xb0000000) /* the block copy hardware */
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/* 0xc0000000 unused */
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/* 0xd0000000 unused */
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/* 0xe0000000 unused */
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#define TME_SUN3_CONTROL_UART_BYPASS (0xf0000000) /* the special UART bypass */
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/* this converts a sun3 control space address into the register number: */
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#define TME_SUN3_CONTROL_REG(address) ((address) >> 28)
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/* this masks a sun3 control space address into a virtual address: */
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#define TME_SUN3_CONTROL_MASK_ADDRESS (0x0ffffffc)
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/* real sun3 enable register bits: */
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#define TME_SUN3_ENA_DIAG (0x01) /* diagnostic switch (read-only) */
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#define TME_SUN3_ENA_FPA (0x02) /* enable FPA */
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#define TME_SUN3_ENA_COPY (0x04) /* enable copy update mode */
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#define TME_SUN3_ENA_VIDEO (0x08) /* enable video display */
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#define TME_SUN3_ENA_CACHE (0x10) /* enable external cache */
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#define TME_SUN3_ENA_SDVMA (0x20) /* enable system DVMA */
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#define TME_SUN3_ENA_FPP (0x40) /* enable 6888x */
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#define TME_SUN3_ENA_NOTBOOT (0x80) /* non-boot state */
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/* real sun3 interrupt register bits: */
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#define TME_SUN3_IREG_INTS_ENAB (0x01) /* enable interrupts */
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#define TME_SUN3_IREG_SOFT_INT_1 (0x02) /* enable level 1 soft interrupts */
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#define TME_SUN3_IREG_SOFT_INT_2 (0x04) /* enable level 2 soft interrupts */
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#define TME_SUN3_IREG_SOFT_INT_3 (0x08) /* enable level 3 soft interrupts */
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#define TME_SUN3_IREG_VIDEO_ENAB (0x10) /* enable video */
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#define TME_SUN3_IREG_CLOCK_ENAB_5 (0x20) /* enable clock interrupts */
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/* 0x40 unused */
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#define TME_SUN3_IREG_CLOCK_ENAB_7 (0x80) /* enable clock NMI interrupts */
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/* real sun3 memory error register parts: */
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#define TME_SUN3_MEMERR_REG_CSR (0)
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#define TME_SUN3_MEMERR_SIZ_CSR (sizeof(tme_uint8_t))
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#define TME_SUN3_MEMERR_REG_VADDR (4)
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#define TME_SUN3_MEMERR_SIZ_VADDR (sizeof(tme_uint32_t))
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#define TME_SUN3_MEMERR_SIZ_REG (TME_SUN3_MEMERR_REG_VADDR + TME_SUN3_MEMERR_SIZ_VADDR)
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/* real sun3 memory error control register bits: */
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#define TME_SUN3_MEMERR_X_INT_ACTIVE (0x80) /* interrupt is active */
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#define TME_SUN3_MEMERR_X_ENABLE_INT (0x40) /* enable memory error interrupts */
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#define TME_SUN3_MEMERR_PAR_TEST (0x20) /* write inverse parity */
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#define TME_SUN3_MEMERR_PAR_ENABLE (0x10) /* enable parity checking */
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#define TME_SUN3_MEMERR_PAR_ERR_BL3 (0x08) /* parity error in D24..D31 */
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#define TME_SUN3_MEMERR_PAR_ERR_BL2 (0x04) /* parity error in D16..D23 */
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#define TME_SUN3_MEMERR_PAR_ERR_BL1 (0x02) /* parity error in D8..D15 */
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#define TME_SUN3_MEMERR_PAR_ERR_BL0 (0x01) /* parity error in D0..D7 */
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/* the page size: */
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#define TME_SUN3_PAGE_SIZE_LOG2 (13)
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#define TME_SUN3_PAGE_SIZE (1 << TME_SUN3_PAGE_SIZE_LOG2)
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/* the number of PMEGs: */
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#define TME_SUN3_PMEGS (256)
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/* the PROM location: */
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#define TME_SUN3_PROM_BASE (0x0FEF0000)
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#define TME_SUN3_PROM_SIZE (0x00010000)
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/* the obio addresses of zs0 and the PROM: */
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#define TME_SUN3_OBIO_ZS0 (0x00020000)
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#define TME_SUN3_OBIO_PROM (0x00100000)
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/* identifiers for the different mainbus connections. the buses are
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together at the beginning of the value space: */
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#define TME_SUN3_CONN_BUS_OBIO (0)
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#define TME_SUN3_CONN_BUS_OBMEM (1)
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#define TME_SUN3_CONN_BUS_VME (2)
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#define TME_SUN3_CONN_BUS_COUNT (3)
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#define TME_SUN3_CONN_OBIO_MASTER (3)
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#define TME_SUN3_CONN_REG_MEMERR (4)
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#define TME_SUN3_CONN_REG_INTREG (5)
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/* the DVMA sizes: */
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#define TME_SUN3_DVMA_SIZE_OBIO (0x01000000)
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#define TME_SUN3_DVMA_SIZE_VME (0x00100000)
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#define TME_SUN3_LOG_HANDLE(sun3) (&(sun3)->tme_sun3_element->tme_element_log_handle)
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/* types: */
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/* a sun3 mainbus connection: */
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struct tme_sun3_bus_connection {
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/* the generic bus connection: */
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struct tme_bus_connection tme_sun3_bus_connection;
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/* what kind of connection this is: */
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unsigned int tme_sun3_bus_connection_which;
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};
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/* a sun3: */
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struct tme_sun3 {
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/* backpointer to our element: */
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struct tme_element *tme_sun3_element;
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/* the IDPROM: */
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tme_uint8_t tme_sun3_idprom_contents[TME_SUN_IDPROM_SIZE];
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/* the MMU: */
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void *tme_sun3_mmu;
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/* the CPU: */
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struct tme_m68k_bus_connection *tme_sun3_m68k;
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/* the different buses: */
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struct tme_bus_connection *tme_sun3_buses[TME_SUN3_CONN_BUS_COUNT];
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#define tme_sun3_obio tme_sun3_buses[TME_SUN3_CONN_BUS_OBIO]
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#define tme_sun3_obmem tme_sun3_buses[TME_SUN3_CONN_BUS_OBMEM]
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#define tme_sun3_vmebus tme_sun3_buses[TME_SUN3_CONN_BUS_VME]
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/* the context register: */
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tme_uint8_t tme_sun3_context;
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/* the enable register: */
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tme_uint8_t tme_sun3_enable;
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/* the UDVMA register: */
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tme_uint8_t tme_sun3_udvma;
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/* the bus error register: */
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tme_uint8_t tme_sun3_buserr;
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/* the diagnostic register: */
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tme_uint8_t tme_sun3_diag;
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/* the interrupt register: */
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tme_uint8_t tme_sun3_ints;
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/* the memory error register: */
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tme_uint8_t tme_sun3_memerr_csr;
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tme_uint32_t tme_sun3_memerr_vaddr;
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unsigned int tme_sun3_memerr_int_asserted;
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struct tme_bus_connection *tme_sun3_memerr_bus;
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/* memory error register test state: */
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struct tme_bus_tlb *tme_sun3_memerr_tlb;
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void *tme_sun3_memerr_cycle_private;
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tme_bus_cycle_handler tme_sun3_memerr_cycle;
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tme_uint8_t tme_sun3_memerr_pending_csr;
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tme_uint32_t tme_sun3_memerr_pending_vaddr;
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/* the interrupt lines that are being asserted: */
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tme_uint8_t tme_sun3_int_signals[(TME_M68K_IPL_MAX + 1 + 7) >> 3];
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/* the last ipl we gave to the CPU: */
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unsigned int tme_sun3_int_ipl_last;
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/* the last clock interrupt bus signal: */
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unsigned int tme_sun3_int_signal_clock_last;
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/* the set of active SDVMA TLB entries: */
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unsigned int tme_sun3_sdvma_tlb_next;
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#define TME_SUN3_SDVMA_TLBS (16)
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struct tme_token *tme_sun3_sdvma_tlb_tokens[TME_SUN3_SDVMA_TLBS];
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/* the m68k bus context register: */
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tme_bus_context_t *tme_sun3_m68k_bus_context;
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};
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/* prototypes: */
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void _tme_sun3_mmu_new _TME_P((struct tme_sun3 *));
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int _tme_sun3_m68k_tlb_fill _TME_P((struct tme_m68k_bus_connection *, struct tme_m68k_tlb *,
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unsigned int, tme_uint32_t, unsigned int));
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int _tme_sun3_bus_tlb_fill _TME_P((struct tme_bus_connection *, struct tme_bus_tlb *,
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tme_bus_addr_t, unsigned int));
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int _tme_sun3_mmu_tlb_set_add _TME_P((struct tme_bus_connection *,
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struct tme_bus_tlb_set_info *));
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int _tme_sun3_mmu_pte_get _TME_P((struct tme_sun3 *, tme_uint32_t, tme_uint32_t *));
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int _tme_sun3_mmu_pte_set _TME_P((struct tme_sun3 *, tme_uint32_t, tme_uint32_t));
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void _tme_sun3_mmu_sdvma_change _TME_P((struct tme_sun3 *));
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void _tme_sun3_mmu_context_set _TME_P((struct tme_sun3 *));
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int _tme_sun3_control_cycle_handler _TME_P((void *, struct tme_bus_cycle *));
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int _tme_sun3_intreg_cycle_handler _TME_P((void *, struct tme_bus_cycle *));
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int _tme_sun3_memerr_cycle_handler _TME_P((void *, struct tme_bus_cycle *));
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int _tme_sun3_memerr_test_cycle_handler _TME_P((void *, struct tme_bus_cycle *));
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int _tme_sun3_ipl_check _TME_P((struct tme_sun3 *));
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#endif /* !_MACHINE_SUN3_IMPL_H */
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