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264 lines
10 KiB
Bash
264 lines
10 KiB
Bash
#! /bin/sh
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# $Id: sparc-misc-auto.sh,v 1.4 2010/02/14 00:29:48 fredette Exp $
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# ic/sparc/sparc-misc-auto.sh - automatically generates C code
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# for miscellaneous SPARC emulation support:
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#
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# Copyright (c) 2005 Matt Fredette
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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# 1. Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# 2. Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution.
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# 3. All advertising materials mentioning features or use of this software
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# must display the following acknowledgement:
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# This product includes software developed by Matt Fredette.
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# 4. The name of the author may not be used to endorse or promote products
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# derived from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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# DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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# INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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#
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header=false
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for option
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do
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case $option in
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--header) header=true ;;
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esac
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done
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PROG=`basename $0`
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cat <<EOF
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/* automatically generated by $PROG, do not edit! */
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EOF
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# emit the register mapping macros:
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if $header; then
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echo ""
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echo "/* the register mapping: */"
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echo "#define TME_SPARC_IREG_UNDEF (-1)"
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ireg_next=0
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# all integer registers start from register number zero:
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#
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for regnum in 0 1 2 3 4 5 6 7; do
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echo "#define TME_SPARC_IREG_G${regnum} (${ireg_next})"
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ireg_next=`expr ${ireg_next} + 1`
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done
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# all other registers start after the last register in the last
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# possible register window:
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#
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ireg_base='(TME_SPARC_WINDOWS_MAX * 16)'
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# the sparc64 alternate, MMU, and interrupt globals:
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#
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echo "#define TME_SPARC64_IREG_AG_G0 (${ireg_base} + ${ireg_next} + (8 * 0))"
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echo "#define TME_SPARC64_IREG_MG_G0 (${ireg_base} + ${ireg_next} + (8 * 1))"
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echo "#define TME_SPARC64_IREG_IG_G0 (${ireg_base} + ${ireg_next} + (8 * 2))"
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ireg_next=`expr ${ireg_next} + 24`
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# the current, next, and next-next program counter:
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#
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echo "#define TME_SPARC_IREG_PC (${ireg_base} + ${ireg_next})"
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ireg_next=`expr ${ireg_next} + 1`
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echo "#define TME_SPARC_IREG_PC_NEXT (${ireg_base} + ${ireg_next})"
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ireg_next=`expr ${ireg_next} + 1`
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echo "#define TME_SPARC_IREG_PC_NEXT_NEXT (${ireg_base} + ${ireg_next})"
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ireg_next=`expr ${ireg_next} + 1`
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# the instruction register:
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#
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echo "#define TME_SPARC_IREG_INSN (${ireg_base} + ${ireg_next})"
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ireg_next=`expr ${ireg_next} + 1`
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# some temporary registers:
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#
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echo "#define TME_SPARC_IREG_TMP(x) (${ireg_base} + ${ireg_next} + (x))"
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ireg_next=`expr ${ireg_next} + 3`
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# the Y multiply/divide register:
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#
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echo "#define TME_SPARC_IREG_Y (${ireg_base} + ${ireg_next})"
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ireg_next=`expr ${ireg_next} + 1`
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# the floating-point transfer registers. since these are often
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# treated as 32-bit parts used to transfer 64- and 128-bit values,
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# this block of registers must be aligned to four. NB that we
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# assume that ${ireg_base} is aligned to at least four:
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#
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while test `expr ${ireg_next} % 4` != 0; do ireg_next=`expr ${ireg_next} + 1`; done
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echo "#define TME_SPARC_IREG_FPX (${ireg_base} + ${ireg_next})"
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ireg_next=`expr ${ireg_next} + 4`
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# the sparc32 PSR, and the sparc64 PSTATE:
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#
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echo "#define TME_SPARC32_IREG_PSR (${ireg_base} + ${ireg_next})"
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echo "#define tme_sparc32_ireg_psr tme_sparc_ireg_uint32(TME_SPARC32_IREG_PSR)"
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echo "#define tme_sparc64_ireg_pstate tme_sparc_ireg_uint32((${ireg_base} + ${ireg_next}) << 1)"
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ireg_next=`expr ${ireg_next} + 1`
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# the sparc32 WIM, and the common sparc64 register-window state registers:
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#
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echo "#define tme_sparc32_ireg_wim tme_sparc_ireg_uint32(${ireg_base} + ${ireg_next})"
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echo "#define tme_sparc64_ireg_winstates tme_sparc_ireg_uint32(((${ireg_base} + ${ireg_next}) << 1) + 0)"
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echo "#define TME_SPARC64_WINSTATES_CWP(x) (((x) & 0x3f) << (8 * 0))"
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echo "#define tme_sparc64_ireg_cwp tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 0)"
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echo "#define TME_SPARC64_WINSTATES_CANRESTORE(x) (((x) & 0x3f) << (8 * 1))"
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echo "#define tme_sparc64_ireg_canrestore tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 1)"
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echo "#define TME_SPARC64_WINSTATES_CANSAVE(x) (((x) & 0x3f) << (8 * 2))"
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echo "#define tme_sparc64_ireg_cansave tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 2)"
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echo "#define TME_SPARC64_WINSTATES_OTHERWIN(x) (((x) & 0x3f) << (8 * 3))"
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echo "#define tme_sparc64_ireg_otherwin tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 3)"
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echo "#define tme_sparc64_ireg_winstates_mask tme_sparc_ireg_uint32(((${ireg_base} + ${ireg_next}) << 1) + 1)"
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ireg_next=`expr ${ireg_next} + 1`
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# the sparc32 TBR register, and the sparc64 TBA register:
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#
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echo "#define tme_sparc32_ireg_tbr tme_sparc_ireg_uint32(${ireg_base} + ${ireg_next})"
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echo "#define tme_sparc64_ireg_tba tme_sparc_ireg_uint64(${ireg_base} + ${ireg_next})"
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ireg_next=`expr ${ireg_next} + 1`
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# the sparc64 trap PC, NPC, state, and type registers:
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#
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echo "#define tme_sparc64_ireg_tpc(tl) tme_sparc_ireg_uint64(${ireg_base} + (TME_SPARC_TL_MAX * 0) + ${ireg_next} + ((tl) - 1))"
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echo "#define tme_sparc64_ireg_tnpc(tl) tme_sparc_ireg_uint64(${ireg_base} + (TME_SPARC_TL_MAX * 1) + ${ireg_next} + ((tl) - 1))"
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echo "#define TME_SPARC64_IREG_TSTATE(tl) (${ireg_base} + (TME_SPARC_TL_MAX * 2) + ${ireg_next} + ((tl) - 1))"
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echo "#define tme_sparc64_ireg_tstate(tl) tme_sparc_ireg_uint64(TME_SPARC64_IREG_TSTATE(tl))"
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echo "#define tme_sparc64_ireg_tstate_ccr(tl) tme_sparc_ireg_uint8((TME_SPARC64_IREG_TSTATE(tl) << 3) + sizeof(tme_uint32_t))"
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echo "#if TME_SPARC_TL_MAX > 8"
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echo "#error \"TME_SPARC_TL_MAX changed\""
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echo "#endif"
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echo "#define tme_sparc64_ireg_tt(tl) tme_sparc_ireg_uint8(((${ireg_base} + (TME_SPARC_TL_MAX * 3) + ${ireg_next}) << 3) + ((tl) - 1))"
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ireg_base="(${ireg_base} + (TME_SPARC_TL_MAX * 3) + 1)"
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# the sparc64 TL, PIL, ASI, FPRS, remaining register-window state registers, and TICK.NPT:
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#
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echo "#define tme_sparc64_ireg_tl tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 0)"
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echo "#define tme_sparc64_ireg_pil tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 1)"
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echo "#define tme_sparc64_ireg_asi tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 2)"
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echo "#define tme_sparc64_ireg_fprs tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 3)"
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echo "#define tme_sparc64_ireg_wstate tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 4)"
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echo "#define tme_sparc64_ireg_cleanwin tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 5)"
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echo "#define tme_sparc64_ireg_tick_npt tme_sparc_ireg_uint8(((${ireg_base} + ${ireg_next}) << 3) + 6)"
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ireg_next=`expr ${ireg_next} + 1`
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# the sparc64 TICK (offset) register:
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#
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echo "#define tme_sparc64_ireg_tick_offset tme_sparc_ireg_uint64(${ireg_base} + ${ireg_next})"
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ireg_next=`expr ${ireg_next} + 1`
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# the sparc64 version register:
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#
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echo "#define tme_sparc64_ireg_ver tme_sparc_ireg_uint64(${ireg_base} + ${ireg_next})"
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ireg_next=`expr ${ireg_next} + 1`
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# the sparc64 CCR:
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# NB: this is a separate register for recode; can it maybe be combined
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# with the block of 8-bit registers above, as the first byte?
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#
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echo "#define TME_SPARC64_IREG_CCR (${ireg_base} + ${ireg_next})"
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echo "#define tme_sparc64_ireg_ccr tme_sparc_ireg_uint8(TME_SPARC64_IREG_CCR << 3)"
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ireg_next=`expr ${ireg_next} + 1`
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# our internal sparc64 RCC register:
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#
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echo "#define TME_SPARC64_IREG_RCC (${ireg_base} + ${ireg_next})"
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ireg_next=`expr ${ireg_next} + 1`
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# our internal virtual address hole start:
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#
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echo "#define tme_sparc64_ireg_va_hole_start tme_sparc_ireg_uint64(${ireg_base} + ${ireg_next})"
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ireg_next=`expr ${ireg_next} + 1`
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fi
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# emit the integer condition codes->conditions mapping. note that the
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# nesting of the flag variables is deliberate, to make this array
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# indexable with the condition codes value:
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#
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if $header; then :; else
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echo ""
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echo "/* the icc->conditions mapping: */"
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echo "const tme_uint8_t _tme_sparc_conds_icc[16] = {"
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for nflag in 0 1; do
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for zflag in 0 1; do
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for vflag in 0 1; do
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for cflag in 0 1; do
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# the Never condition:
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#
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echo -n " 0"
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# the Equal condition:
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#
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if test $zflag = 1; then
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echo -n " | TME_BIT(1)"
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fi
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# the Less or Equal condition:
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#
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if test $zflag = 1 || test $nflag != $vflag; then
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echo -n " | TME_BIT(2)"
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fi
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# the Less condition:
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#
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if test $nflag != $vflag; then
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echo -n " | TME_BIT(3)"
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fi
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# the Less or Equal Unsigned condition:
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#
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if test $cflag = 1 || test $zflag = 1; then
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echo -n " | TME_BIT(4)"
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fi
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# the Carry Set condition:
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#
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if test $cflag = 1; then
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echo -n " | TME_BIT(5)"
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fi
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# the Negative condition:
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#
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if test $nflag = 1; then
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echo -n " | TME_BIT(6)"
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fi
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# the Overflow Set condition:
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#
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if test $vflag = 1; then
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echo -n " | TME_BIT(7)"
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fi
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echo ","
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done
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done
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done
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done
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echo "};"
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fi
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# done:
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#
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exit 0
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