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440 lines
19 KiB
C
440 lines
19 KiB
C
/* $Id: sun4-impl.h,v 1.3 2009/08/30 14:01:55 fredette Exp $ */
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/* machine/sun4/sun4-impl.h - implementation header file for Sun 4 emulation: */
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/*
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* Copyright (c) 2005, 2006 Matt Fredette
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Matt Fredette.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MACHINE_SUN4_IMPL_H
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#define _MACHINE_SUN4_IMPL_H
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#include <tme/common.h>
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_TME_RCSID("$Id: sun4-impl.h,v 1.3 2009/08/30 14:01:55 fredette Exp $");
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/* includes: */
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#include <tme/generic/bus.h>
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#include <tme/machine/sun.h>
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#include <tme/ic/sparc.h>
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#include <tme/element.h>
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#include <sys/types.h>
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#include <sys/time.h>
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/* macros: */
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/* real sun4 ASIs: */
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/* 0x00 unused */
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/* 0x01 unused */
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#define TME_SUN4_32_ASI_CONTROL (0x02) /* all 32-bit sun4: control space */
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#define TME_SUN44C_ASI_SEGMAP (0x03) /* sun4/4c: the segment map */
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#define TME_SUN44C_ASI_PGMAP (0x04) /* sun4/4c: the page map */
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#define TME_SUN4_ASI_COPY (0x05) /* sun4: block copy */
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#define TME_SUN4C_ASI_HW_FLUSH_SEG (0x05) /* sun4c: hardware-assisted flush segment */
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#define TME_SUN4_ASI_REGMAP (0x06) /* sun4: region map */
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#define TME_SUN4C_ASI_HW_FLUSH_PG (0x06) /* sun4c: hardware-assisted flush page */
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#define TME_SUN4_ASI_FLUSH_REG (0x07) /* sun4: flush region */
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#define TME_SUN4C_ASI_HW_FLUSH_CONTEXT (0x07) /* sun4c: hardware-assisted flush context */
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/* 0x08 is TME_SPARC32_ASI_UI */
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/* 0x09 is TME_SPARC32_ASI_SI */
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/* 0x0a is TME_SPARC32_ASI_UD */
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/* 0x0b is TME_SPARC32_ASI_SD */
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#define TME_SUN44C_ASI_FLUSH_SEG (0x0c) /* sun4/4c: flush segment */
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#define TME_SUN44C_ASI_FLUSH_PG (0x0d) /* sun4/4c: flush page */
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#define TME_SUN44C_ASI_FLUSH_CONTEXT (0x0e) /* sun4/4c: flush context */
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#define TME_SUN4_ASI_FLUSH_USER (0x0f) /* sun4: flush user */
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#define TME_SUN4C_ASI_HW_FLUSH_ALL (0x0f) /* sun4c: hardware-assisted flush all */
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#define TME_SUN4_32_ASI_COUNT (0x3a) /* all 32-bit sun4: count of ASIs */
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/* real sun4 ASI_CONTROL space addresses: */
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#define TME_SUN4_CONTROL_IDPROM (0x00000000) /* sun4: the IDPROM */
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/* 0x10000000 was the sun3 page map */
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/* 0x20000000 was the sun3 segment map */
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#define TME_SUN44C_CONTROL_CONTEXT (0x30000000) /* sun4/4c: the context register */
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#define TME_SUN44C_CONTROL_ENABLE (0x40000000) /* sun4/4c: the enable register */
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#define TME_SUN4_CONTROL_UDVMA (0x50000000) /* sun4: the user DVMA enable register */
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#define TME_SUN4_CONTROL_BUSERR (0x60000000) /* sun4: the bus error register */
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#define TME_SUN4C_CONTROL_SYNC_ERR (0x60000000) /* sun4c: the synchronous error register */
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#define TME_SUN4C_CONTROL_SYNC_VADDR (0x60000004) /* sun4c: the synchronous error virtual address register */
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#define TME_SUN4C_CONTROL_ASYNC_ERR (0x60000008) /* sun4c: the asynchronous error register */
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#define TME_SUN4C_CONTROL_ASYNC_VADDR (0x6000000c) /* sun4c: the asynchronous error virtual address register */
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#define TME_SUN4C_CONTROL_ASYNC_DATA_LO (0x60000010) /* sun4c: the asynchronous error low data register */
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#define TME_SUN4C_CONTROL_ASYNC_DATA_HI (0x60000014) /* sun4c: the asynchronous error low data register */
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#define TME_SUN4_CONTROL_DIAG (0x70000000) /* sun4: the diagnostic register */
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#define TME_SUN44C_CONTROL_CACHE_TAGS (0x80000000) /* sun4/4c: the VAC tags */
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#define TME_SUN44C_CONTROL_CACHE_DATA (0x90000000) /* sun4/4c: the VAC data */
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/* 0xa0000000 was the sun3 VAC flush */
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/* 0xb0000000 was the sun3 block copy hardware */
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/* 0xc0000000 unused */
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#define TME_SUN4_CONTROL_UDVMA_MAP (0xd0000000) /* sun4: the user DVMA map */
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#define TME_SUN4_CONTROL_VME_INTVEC (0xe0000000) /* sun4: the VME interrupt vector */
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#define TME_SUN44C_CONTROL_UART_BYPASS (0xf0000000) /* sun4/4c: the special UART bypass */
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/* this converts a sun4/4c control space address into the register number: */
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#define TME_SUN44C_CONTROL_REG(address) ((address) >> 28)
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/* real sun4/4c enable register bits: */
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#define TME_SUN4_ENA_DIAG (0x01) /* sun4: diagnostic switch (read-only) */
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#define TME_SUN4_ENA_MONITOR (0x01) /* sun4: "monitor bit" (write-only) */
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#define TME_SUN4_ENA_RESET_VME (0x02) /* sun4: reset the VME bus */
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#define TME_SUN4_ENA_RESET_CACHE (0x04) /* sun4: reset the cache */
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#define TME_SUN4C_ENA_RESET_SW (0x04) /* sun4c: software reset */
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#define TME_SUN4_ENA_VIDEO (0x08) /* sun4: enable video display */
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#define TME_SUN44C_ENA_CACHE (0x10) /* sun4/4c: enable external cache */
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#define TME_SUN44C_ENA_SDVMA (0x20) /* sun4/4c: enable system DVMA */
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#define TME_SUN4_ENA_IOCACHE (0x40) /* sun4: enable the I/O cache */
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#define TME_SUN44C_ENA_NOTBOOT (0x80) /* sun4/4c: non-boot state */
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/* real sun4/4c interrupt register bits: */
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#define TME_SUN44C_IREG_INTS_ENAB (0x01) /* sun4/4c: enable interrupts */
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#define TME_SUN44C_IREG_SOFT_INT_L1 (0x02) /* sun4/4c: enable level 1 soft interrupts */
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#define TME_SUN44C_IREG_SOFT_INT_L4 (0x04) /* sun4/4c: enable level 4 soft interrupts */
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#define TME_SUN44C_IREG_SOFT_INT_L6 (0x08) /* sun4/4c: enable level 6 soft interrupts */
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#define TME_SUN44C_IREG_VIDEO_INT (0x10) /* sun4/4c: enable level 8 video interrupts */
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#define TME_SUN44C_IREG_COUNTER_L10 (0x20) /* sun4/4c: enable counter0 level 10 interrupts */
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/* 0x40 unused */
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#define TME_SUN44C_IREG_COUNTER_L14 (0x80) /* sun4/4c: enable counter1 level 14 interrupts */
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/* real sun4/4c memory error register parts: */
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#define TME_SUN44C_MEMERR_REG_CSR (0)
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#define TME_SUN44C_MEMERR_SIZ_CSR (sizeof(tme_uint32_t))
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#define TME_SUN4C_MEMERR_REG_PARCTL (4)
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#define TME_SUN4C_MEMERR_SIZ_PARCTL (sizeof(tme_uint32_t))
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#define TME_SUN4_MEMERR_REG_VADDR (4)
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#define TME_SUN4_MEMERR_SIZ_VADDR (sizeof(tme_uint32_t))
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#define TME_SUN44C_MEMERR_SIZ_REG (TME_SUN4_MEMERR_REG_VADDR + TME_SUN4_MEMERR_SIZ_VADDR)
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/* real sun4/4c parity and ECC memory error control register bits: */
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#define TME_SUN4_MEMERR_X_CONTEXT_MASK (0x1fe00) /* sun4: context mask */
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#define TME_SUN4_MEMERR_X_DVMA (0x100) /* sun4: access was DVMA */
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#define TME_SUN4_MEMERR_X_INT_ACTIVE (0x80) /* sun4: interrupt is active */
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#define TME_SUN4C_MEMERR_PAR_ERROR (0x80) /* sun4c: parity error detected */
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#define TME_SUN4_MEMERR_X_ENABLE_INT (0x40) /* sun4: enable memory error interrupts */
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#define TME_SUN4C_MEMERR_PAR_MULTI (0x40) /* sun4c: multiple parity errors detected */
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#define TME_SUN44C_MEMERR_PAR_TEST (0x20) /* sun4/4c: write inverse parity */
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#define TME_SUN44C_MEMERR_PAR_ENABLE (0x10) /* sun4/4c: enable parity checking */
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#define TME_SUN44C_MEMERR_PAR_ERR_BL3 (0x08) /* sun4/4c: parity error in (sun4) D24..D31 (sun4c) D0..D7 */
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#define TME_SUN44C_MEMERR_PAR_ERR_BL2 (0x04) /* sun4/4c: parity error in (sun4) D16..D23 (sun4c) D8..D15 */
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#define TME_SUN44C_MEMERR_PAR_ERR_BL1 (0x02) /* sun4/4c: parity error in (sun4) D8..D15 (sun4c) D16..D23 */
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#define TME_SUN44C_MEMERR_PAR_ERR_BL0 (0x01) /* sun4/4c: parity error in (sun4) D0..D7 (sun4c) D24..D31 */
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/* real sun4/4c/4m timer register parts: */
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#define TME_SUN4_32_TIMER_REG_COUNTER (0)
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#define TME_SUN4_32_TIMER_SIZ_COUNTER (sizeof(tme_uint32_t))
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#define TME_SUN4_32_TIMER_REG_LIMIT (TME_SUN4_32_TIMER_REG_COUNTER + TME_SUN4_32_TIMER_SIZ_COUNTER)
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#define TME_SUN4_32_TIMER_SIZ_LIMIT (sizeof(tme_uint32_t))
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#define TME_SUN44C_TIMER_SIZ_REG (TME_SUN4_32_TIMER_REG_LIMIT + TME_SUN4_32_TIMER_SIZ_LIMIT)
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/* the page sizes: */
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#define TME_SUN4_PAGE_SIZE_LOG2 (13)
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#define TME_SUN4_PAGE_SIZE (1 << TME_SUN4_PAGE_SIZE_LOG2)
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#define TME_SUN4C_PAGE_SIZE_LOG2 (12)
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#define TME_SUN4C_PAGE_SIZE (1 << TME_SUN4C_PAGE_SIZE_LOG2)
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/* all 32-bit sun4s have the same segment size: */
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#define TME_SUN4_32_SEGMENT_SIZE_LOG2 (18)
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#define TME_SUN4_32_SEGMENT_SIZE (1 << TME_SUN4_32_SEGMENT_SIZE_LOG2)
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/* real sun4/4c PTE entry bits: */
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#define TME_SUN44C_PTE_VALID (0x80000000)
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#define TME_SUN44C_PTE_WRITE (0x40000000)
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#define TME_SUN44C_PTE_SYSTEM (0x20000000)
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#define TME_SUN44C_PTE_NC (0x10000000)
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#define TME_SUN44C_PTE_PGTYPE (0x0C000000)
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#define TME_SUN44C_PTE_REF (0x02000000)
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#define TME_SUN44C_PTE_MOD (0x01000000)
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#define TME_SUN4_PTE_PGFRAME (0x0007FFFF)
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#define TME_SUN4C_PTE_PGFRAME (0x0000FFFF)
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/* the PROM location: */
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#define TME_SUN44C_PROM_BASE (0xF6000000)
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#define TME_SUN44C_PROM_SIZE (0x00040000)
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/* the obio addresses of zs0 and zs1: */
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#define TME_SUN44C_OBIO_ZS0 (0xf1000000)
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/* the obio address of the start of the SBus slots: */
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#define TME_SUN4C_OBIO_SBUS (0xf8000000)
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/* identifiers for the different board bus connections. the buses are
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together at the beginning of the value space: */
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#define TME_SUN4_32_CONN_BUS_OBIO (0)
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#define TME_SUN4_32_CONN_BUS_OBMEM (1)
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#define TME_SUN4_CONN_BUS_VME (2)
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#define TME_SUN4_32_CONN_BUS_COUNT (3)
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#define TME_SUN4_32_CONN_REG_TIMER (3)
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#define TME_SUN4_32_CONN_REG_MEMERR (4)
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#define TME_SUN4_32_CONN_REG_INTREG (5)
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#define TME_SUN4C4M_CONN_REG_AUXREG (6)
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#define TME_SUN4_32_CONN_REG_COUNT (7)
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/* the DVMA sizes: */
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#define TME_SUN4_DVMA_SIZE_VME (0x00100000)
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/* these return nonzero on a match of the IDPROM machine type byte: */
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#define TME_SUN4_IS_ARCH(sun4, arch) \
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(((sun4)->tme_sun4_idprom_contents[TME_SUN_IDPROM_OFF_MACHTYPE] & TME_SUN_IDPROM_TYPE_MASK_ARCH) == (arch))
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#define TME_SUN4_IS_MODEL(sun4, model) \
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((sun4)->tme_sun4_idprom_contents[TME_SUN_IDPROM_OFF_MACHTYPE] == (model))
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#define TME_SUN4_IS_SUN4(sun4) TME_SUN4_IS_ARCH(sun4, TME_SUN_IDPROM_TYPE_ARCH_SUN4)
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#define TME_SUN4_IS_SUN4C(sun4) TME_SUN4_IS_ARCH(sun4, TME_SUN_IDPROM_TYPE_ARCH_SUN4C)
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#define TME_SUN4_IS_SUN44C(sun4) TRUE
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#define TME_SUN4_IS_SUN4M(sun4) FALSE
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#define TME_SUN4_IS_SUN4C4M(sun4) (TME_SUN4_IS_SUN4C(sun4) || TME_SUN4_IS_SUN4M(sun4))
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/* this returns the MMU context used by a particular bus connection: */
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#define TME_SUN44C_BUS_MMU_CONTEXT(sun4, conn_bus) ((sun4)->tme_sun44c_context)
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/* these returns nonzero if memory error testing is visible: */
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/* on the sun4/4c, memory error testing is visible if there are any
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bad addresses and parity checking is enabled, or if bad parity
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writing is enabled: */
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#define TME_SUN44C_MEMERR_VISIBLE(sun4) \
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((sun4)->tme_sun4_memerr_bad_memory_count > 0 \
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|| (((sun4)->tme_sun44c_memerr_csr[0] \
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| (sun4)->tme_sun44c_memerr_csr[1]) \
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& TME_SUN44C_MEMERR_PAR_TEST) != 0)
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#define TME_SUN4_LOG_HANDLE(sun4) (&(sun4)->tme_sun4_element->tme_element_log_handle)
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/* types: */
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/* a sun4 bus connection: */
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struct tme_sun4_bus_connection {
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/* the generic bus connection: */
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struct tme_bus_connection tme_sun4_bus_connection;
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/* what kind of connection this is: */
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unsigned int tme_sun4_bus_connection_which;
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};
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/* a sun4 timer: */
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struct tme_sun4_timer {
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/* a backpointer to the sun4: */
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struct tme_sun4 *tme_sun4_timer_sun4;
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/* the real counter and limit register values: */
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tme_uint32_t tme_sun4_timer_counter;
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tme_uint32_t tme_sun4_timer_limit;
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/* the period of this timer: */
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struct timeval tme_sun4_timer_period;
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/* when the timer reaches its next limit: */
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struct timeval tme_sun4_timer_limit_next;
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/* a condition for waking up the thread for this timer: */
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tme_cond_t tme_sun4_timer_cond;
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/* this is nonzero if the interrupt for this timer is asserted: */
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unsigned int tme_sun4_timer_int_asserted;
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/* these are used to track the interrupt rate for this timer: */
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tme_uint32_t tme_sun4_timer_track_ints;
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struct timeval tme_sun4_timer_track_sample;
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};
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/* a sun4: */
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struct tme_sun4 {
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/* our mutex: */
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tme_mutex_t tme_sun4_mutex;
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/* backpointer to our element: */
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struct tme_element *tme_sun4_element;
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/* the IDPROM: */
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tme_uint8_t tme_sun4_idprom_contents[TME_SUN_IDPROM_SIZE];
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/* the CPU: */
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struct tme_sparc_bus_connection *tme_sun4_sparc;
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/* a set of bus connections: */
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struct tme_bus_connection *tme_sun4_buses[TME_SUN4_32_CONN_REG_COUNT];
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#define tme_sun4_32_obio tme_sun4_buses[TME_SUN4_32_CONN_BUS_OBIO]
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#define tme_sun4_32_obmem tme_sun4_buses[TME_SUN4_32_CONN_BUS_OBMEM]
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#define tme_sun4_vmebus tme_sun4_buses[TME_SUN4_CONN_BUS_VME]
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/* these dummy bus connection structures are used to thread bus
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information to bus error handlers: */
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struct tme_connection tme_sun4_dummy_connection_sparc;
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/* these structures are used to thread ASI information to a control
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cycle handler. if the backpointer for an ASI is NULL, the ASI is
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undefined: */
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struct tme_sun4_asi {
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struct tme_sun4 *tme_sun4_asi_sun4;
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} tme_sun4_asis[TME_SUN4_32_ASI_COUNT];
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/* the current TLB fill function: */
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int (*tme_sun4_tlb_fill) _TME_P((const struct tme_bus_connection *,
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struct tme_bus_tlb *,
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tme_uint32_t *,
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tme_uint32_t,
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unsigned int));
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/* visible memory test support: */
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struct tme_bus_tlb *tme_sun4_memtest_tlb;
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tme_uint32_t tme_sun4_memtest_tlb_asi_mask;
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/* cache support: */
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unsigned int tme_sun4_cache_size_log2;
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unsigned int tme_sun4_cache_size_line_log2;
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unsigned int tme_sun4_cache_writeback;
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tme_shared tme_uint8_t *tme_sun4_cache_data;
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tme_rwlock_t tme_sun4_cache_rwlock;
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tme_uint32_t tme_sun4_cache_visible;
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struct tme_bus_tlb tme_sun4_cache_tlb_internal;
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struct tme_token tme_sun4_cache_tlb_internal_token;
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/* memory error support: */
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unsigned int tme_sun4_memerr_int_asserted;
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const tme_shared tme_uint8_t *tme_sun4_memerr_bad_memory[128];
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unsigned int tme_sun4_memerr_bad_memory_count;
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const tme_shared tme_uint8_t *tme_sun4_memerr_tlb_emulator_off_read;
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tme_shared tme_uint8_t *tme_sun4_memerr_tlb_emulator_off_write;
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/* timer support: */
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unsigned int tme_sun4_timer_callouts_running;
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struct tme_sun4_timer tme_sun4_timers[2];
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#define tme_sun4_timer_l10 tme_sun4_timers[0]
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#define tme_sun4_timer_l14 tme_sun4_timers[1]
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/* the sun4/4c MMU and context register: */
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void *tme_sun44c_mmu;
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tme_uint32_t tme_sun44c_mmu_pmegs;
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tme_uint8_t tme_sun44c_context;
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/* the sun4/4c enable register: */
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tme_uint8_t tme_sun44c_enable;
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/* the sun4/4c UDVMA register: */
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tme_uint8_t tme_sun4_udvma;
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/* the sun4 bus error register: */
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tme_uint8_t tme_sun4_buserr;
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/* the sun4 diagnostic register: */
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tme_uint8_t tme_sun4_diag;
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/* the sun4/4c interrupt register: */
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tme_uint8_t tme_sun44c_ints;
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/* the sun4c/4m auxiliary register: */
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tme_uint8_t tme_sun4c4m_aux;
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/* the sun4/4c cache: */
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tme_uint32_t *tme_sun44c_cache_tags;
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/* the sun4c synchronous and asynchronous error registers: */
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tme_uint32_t tme_sun4c_sync_err;
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tme_uint32_t tme_sun4c_sync_vaddr;
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tme_uint32_t tme_sun4c_async_err;
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tme_uint32_t tme_sun4c_async_vaddr;
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tme_uint32_t tme_sun4c_async_data_lo;
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tme_uint32_t tme_sun4c_async_data_hi;
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/* the sun4/4c memory error registers: */
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tme_uint32_t tme_sun44c_memerr_csr[2];
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tme_uint32_t tme_sun4c_memerr_parctl[2];
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tme_uint32_t tme_sun4_memerr_vaddr;
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/* the interrupt lines that are being asserted: */
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tme_uint8_t tme_sun4_int_signals[(TME_SPARC_IPL_MAX + 1 + 7) >> 3];
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/* the last ipl we gave to the CPU: */
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unsigned int tme_sun4_int_ipl_last;
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/* the set of active sun4/4c SDVMA TLB entries: */
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unsigned int tme_sun44c_sdvma_tlb_next;
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#define TME_SUN44C_SDVMA_TLBS (16)
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struct tme_token *tme_sun44c_sdvma_tlb_tokens[TME_SUN44C_SDVMA_TLBS];
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/* the sun4/4c sparc v7 bus context register: */
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tme_bus_context_t *tme_sun44c_sparc_bus_context;
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};
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/* sun4/4c cache prototypes: */
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void _tme_sun44c_cache_new _TME_P((struct tme_sun4 *));
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void _tme_sun44c_cache_enable_change _TME_P((struct tme_sun4 *));
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int _tme_sun44c_cache_cycle_control _TME_P((struct tme_sun4 *, struct tme_bus_cycle *));
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void _tme_sun44c_cache_cycle_flush _TME_P((struct tme_sun4 *sun4, tme_uint32_t, tme_uint32_t));
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/* sun4/4c memory error prototypes: */
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int _tme_sun44c_memerr_cycle_control _TME_P((void *, struct tme_bus_cycle *));
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int _tme_sun44c_memerr_cycle_bus _TME_P((void *, struct tme_bus_cycle *));
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int _tme_sun44c_memerr_check _TME_P((const struct tme_bus_connection *, tme_uint32_t, tme_uint32_t, const tme_shared tme_uint8_t *, unsigned int));
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void _tme_sun44c_memerr_update _TME_P((struct tme_sun4 *, tme_uint32_t, const tme_shared tme_uint8_t *, unsigned int));
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int _tme_sun44c_tlb_fill_memerr _TME_P((const struct tme_bus_connection *,
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struct tme_bus_tlb *,
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tme_uint32_t *,
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tme_uint32_t,
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unsigned int));
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/* sun4/4c MMU prototypes: */
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void _tme_sun44c_mmu_new _TME_P((struct tme_sun4 *));
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int _tme_sun44c_mmu_tlb_set_add _TME_P((struct tme_bus_connection *,
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struct tme_bus_tlb_set_info *));
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void _tme_sun44c_mmu_sdvma_change _TME_P((struct tme_sun4 *));
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void _tme_sun44c_mmu_context_set _TME_P((struct tme_sun4 *));
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int _tme_sun44c_mmu_pte_get _TME_P((struct tme_sun4 *, tme_uint32_t, tme_uint32_t *));
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int _tme_sun44c_mmu_pte_set _TME_P((struct tme_sun4 *, tme_uint32_t, tme_uint32_t));
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int _tme_sun44c_mmu_proterr _TME_P((void *, struct tme_bus_cycle *));
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int _tme_sun44c_tlb_fill_sparc _TME_P((struct tme_sparc_bus_connection *,
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struct tme_sparc_tlb *,
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tme_uint32_t asi_mask,
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tme_bus_addr_t address,
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unsigned int cycles));
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int _tme_sun44c_tlb_fill_bus _TME_P((struct tme_bus_connection *,
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struct tme_bus_tlb *,
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tme_bus_addr_t,
|
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unsigned int));
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int _tme_sun44c_tlb_fill_mmu _TME_P((const struct tme_bus_connection *,
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struct tme_bus_tlb *,
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tme_uint32_t *,
|
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tme_uint32_t,
|
|
unsigned int));
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int _tme_sun44c_ob_fault_handler _TME_P((void *, struct tme_bus_tlb *, struct tme_bus_cycle *, int));
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/* timer prototypes: */
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void _tme_sun4_timer_new _TME_P((struct tme_sun4 *));
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int _tme_sun4_timer_cycle_control _TME_P((void *, struct tme_bus_cycle *));
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void _tme_sun4_timer_int_force _TME_P((struct tme_sun4 *, struct tme_sun4_timer *));
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/* other prototypes: */
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int _tme_sun44c_control_cycle_handler _TME_P((void *, struct tme_bus_cycle *));
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int _tme_sun44c_intreg_cycle_control _TME_P((void *, struct tme_bus_cycle *));
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int _tme_sun4c_auxreg_cycle_control _TME_P((void *, struct tme_bus_cycle *));
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int _tme_sun4_ipl_check _TME_P((struct tme_sun4 *));
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int _tme_sun4_reset _TME_P((struct tme_sun4 *, int));
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#endif /* !_MACHINE_SUN4_IMPL_H */
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